Cadence公司的数字IC设计工具：综合工具（Genus）——（1）

目录

一、Genus入门

1、用户接口

1.1 Unified User Interface

1.2 Legacy User Interface

2、log file

3、Navigation

4、输出重定向

5、脚本

二、Genus综合流程

1、Set Search Paths and Target Lbrary

1.1 Specifying explicit search paths

1.1.1 technology libraries

1.1.2 scritps

1.1.3 HDL files

1.2 Setting the target technology library

1.2.1  Specify single library

1.2.2 Specify multiple libraries

2、Load HDL Files

2.1 Reading HDL files

2.2 read_hdl命令的命令行选项

2.3 read and elaborating a structural netlist design

3、Perform Elaboration

3.1 performing elaboration

4、Apply Constraints

4.1 importing and exporting SDC

4.2 applying timing constraints

4.2.1 Specifying clock information

4.2.1.1 defining a clock / the clock period / the rising and falling edges and creating clock domains

4.2.1.2 specifying clock latency (insertion delay)

4.2.1.3 specifying clock skew

4.2.1.4 Specifying the clock transition

4.2.1.5 Defining Externally Generated Clocks

4.2.2 defining input and output delays

4.2.3 setting timing exceptions

4.2.3.1 false path

4.2.3.2 Multicycle paths

4.2.3.3 paths delays

4.3 importing physical information

4.4 applying design rule constraints

4.4.1 specifying operating conditions

4.4.2 specifying wire-load models

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