EDA开源仿真工具verilator入门10:verilator 实现vcd波形保存

verilog文件：multi_logic.v

module multi_logic (a,clk,ou1);input a,clk;output ou1;      reg a, clk, ou1;           always @(posedge clk) beginou1 <= a;end
endmodule

cpp文件：test_main.cpp

#include 
#include 
#include #include "Vmulti_logic.h"  // create `multi_logic.v`,so use `Vmulti_logic.h`
#include "verilated.h"#include "verilated_vcd_c.h" //可选，如果要导出vcd则需要加上int main(int argc, char** argv, char** env) {VerilatedContext* contextp = new VerilatedContext;contextp->commandArgs(argc, argv);Vmulti_logic* multiLogic = new Vmulti_logic{contextp};VerilatedVcdC* tfp = new VerilatedVcdC; //初始化VCD对象指针contextp->traceEverOn(true); //打开追踪功能multiLogic->trace(tfp, 0); //tfp->open("wave.vcd"); //设置输出的文件wave.vcdint clk = 0;int count = 0;int clkin = 1;multiLogic->a = 0;//multiLogic->b = 0;multiLogic->clk = clkin;while (!contextp->gotFinish()) {contextp->timeInc(1); //推动仿真时间count++;int a = rand() & 1;int b = rand() & 1;clk = !clk;clkin = clk;multiLogic->clk = clkin;multiLogic->a = a;//multiLogic->b = b;multiLogic->eval();if (clk)printf("a = %d, ou1 = %d\n",a, multiLogic->ou1);tfp->dump(contextp->time()); //dump waveif (count > 30) break;}delete multiLogic;tfp->close();delete contextp;return 0;
}

verilator编译指令：

verilator -Wall --trace --cc --exe --build multi_logic.v test_main.cpp

注意要加上--trace参数，执行仿真程序，会生成对应的vcd波形文件，可以用gtkwave查看。我们来查看vcd文件格式：

$version Generated by VerilatedVcd $end
$date Mon Apr  3 23:52:15 2023 $end
$timescale 1ps $end$scope module TOP $end$var wire  1 # a $end$var wire  1 $ clk $end$var wire  1 % ou1 $end$scope module multi_logic $end$var wire  1 # a $end$var wire  1 $ clk $end$var wire  1 % ou1 $end$upscope $end$upscope $end
$enddefinitions $end#1
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