SSC CC SRNS SRIS PPM
- SSC - Spread Spectrum Clocking 扩频时钟技术主要是用来降低EMI。
- CC - Common Clocked architectures (CC)
- SRIS - Separate Refclk Independent SSC.
- SRNS - Separate Refclk with No SSC。
PCIe Clocking Architectures The PCIe standard specifies a 100 MHz clock (Refclk) with at least ±300 ppm frequency stability for Gen 1, 2, 3 and 4, and at least ±100 ppm frequency stability for Gen 5, at both the transmitting and receiving devices.
SRNS允许600ppm，而SRIS允许5600ppm（其中SSC允许5000ppm（单向展频0.5%，0.5/100=0.005*100 0000ppm=5000ppm），TX/RX允许600ppm）
如果使用SSC所有使用SSC芯片的时钟必须同源
如果不使用SSC，各芯片的时钟不要求同源
PPM计算方法：
ppm是百万分之一,我用的晶振是74.25MHz,实际用频率计测量是74.24MHz，晶振的误差是（74.24-74.25）/74.25≈0.000135=135*10^-6
误差是135ppm
HBW_BYPASS_LBW
In PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive
cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs.
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