python verilog顶层连线,如何在Verilog中连接两个模块？
I have written two modules DLatch and RSLatch and i want to write verilog code to join those two.
解决方案
Seriously, you should get yourself a Verilog handbook or search for some online resources.
Anyway, something like this should work:
module dff (
input Clk,
input D,
output Q,
output Qbar
);
wire q_to_s;
wire qbar_to_r;
wire clk_bar;
assign clk_bar = ~Clk;
D_latch dlatch (
.D(D),
.Clk(Clk),
.Q(q_to_s),
.Qbar(qbar_to_r)
);
RS_latch rslatch (
.S(q_to_s),
.R(qbar_to_r),
.Clk(clk_bar),
.Qa(Q),
.Qb(Qbar)
);
endmodule
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