MCP Features

MCP: Multiple Chip Package, 
          MCP是在一个塑料封装外壳内，垂直堆叠大小不同的各类存储器或非存储器芯片，是一种一级单封装的混合技术，用此方法节约小巧印刷电路板PCB空间。

MCP由 Nand-flash 和 LPDDRx组成。

Nand-flash 主要参数：
> SLC/MLC/TLC technology
> Total  size (Device size)
> Block size
> Page size, Spare size
> Array performance
   operation time for Read page: 25us
   operation time for Program page： 200us
   operation time for Program page ECC ON： 240us
   operation time for Erase block: 2ms
> OTP （One-Time Programmable Mode) 
> Block lock
> Block lock tight (permanently locked/unlocked, freeze the lock status)
> Programmable drive strength
> Read unique ID
> Internal data move
> RESET (FFh) required as first command after power-on

> 总线接口协议
   ONFI Nand flash protocol

• Quality and reliability
– Endurance: 100,000 PROGRAM/ERASE cycles IT temperature range
– Endurance: 60,000 PROGRAM/ERASE cycles AT temperature range
– Data retention: JESD47G-compliant; see qualification report
• Additional: Uncycled data retention: 10 years 24/7 @ 85°C

LPDDRx主要特性&参数：
> Self refresh (full array)
> Partitial-array self refresh  (1/2, 1/4, 1/8 array )
> DPD (Deep Power Down)
> Selectable output drive strength
> Adjustable clock frequency

Notes: When TC >105°C: Self refresh mode is not available.

Self Refresh
      |------------ Distributed refresh pattern (refresh period 7.8us)
      L----------- Burst refresh pattern (refresh period 0.52us, but can have ~32ms without any refresh command)

Power Down Mode
      |------------ Idle power down
      L----------- Active power down (there exists a row active in any bank)
Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. In power-down mode, CKE must be held LOW; all other input signals.

Deep Power Down
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry are disabled within the device.  The contents of the array will be lost upon entering DPD mode.

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