一、AD7606模块参数
AD型号：AD7606
通道数：8通道
AD位数：16bit
最高采样频率:200ksps
输入电压：-5V~+5V
二、模块结构
三、AD7607简介
AD7606是一款8通道同步采样数据采集系统，片内集成输入放大器，过压保护电路，二阶模拟抗混叠滤波器、模拟多路复用器、16位200KPS SARADC和一个数字滤波器，2.5V基准电压源。
可以处理 ±10V与±5V真双极性输入信号。
四、AD7606功能图
五、AD7606时序图
AD7606可以对所有8路的模拟输入通道同步采样。当两个CONVST引脚（CONVSTA和CONVSTB）连在一起的时，所有通道同步采样。此共用CONVST信息的上升沿启动对所有模拟输入通道的同步采样（V1至V8）。
BUSY信息告知用户正在进行转换，因此当施加CONVST上升沿时，BUSY变为逻辑高电平，在整个转换过程结束时变成低电平。BUSY信号下降沿用来使所有八个采样保持放大器返回跟踪模式。BUSY下降沿还表示可以从并行总线DB[15:0]读取8个通道的数据。
AD7606的模拟输入信号为±5V或±10V，当**±5V输入范围时，1LSB=152.58uV**，当设置为**±10V输入范围，1LSB=305.175uV**。
ADC7606输出为二进制补码，ADC7606的LSB大小为FSR/65536，
六、接口定义
实验
一、在D:\4workspace\7020_Verilog\下新建“12_adc7606”文件
新建工程12_adc7606
选择器件型号点击完成
分别新建文件
新建如下文件并添加代码
顶层文件ad706_test.v
`timescale 1ns / 1ps
//
// Module Name: ad706_test
//
module ad706_test(input clk, //50mhzinput rst_n,input [15:0] ad_data, //ad7606 采样数据input ad_busy, //ad7606 忙标志位 input first_data, //ad7606 第一个数据标志位 output [2:0] ad_os, //ad7606 过采样倍率选择output ad_cs, //ad7606 AD csoutput ad_rd, //ad7606 AD data readoutput ad_reset, //ad7606 AD resetoutput ad_convstab, //ad7606 AD convert startinput rx,output tx);wire [15:0] ad_ch1;
wire [15:0] ad_ch2;
wire [15:0] ad_ch3;
wire [15:0] ad_ch4;
wire [15:0] ad_ch5;
wire [15:0] ad_ch6;
wire [15:0] ad_ch7;
wire [15:0] ad_ch8;wire [19:0] ch1_dec;
wire [19:0] ch2_dec;
wire [19:0] ch3_dec;
wire [19:0] ch4_dec;
wire [19:0] ch5_dec;
wire [19:0] ch6_dec;
wire [19:0] ch7_dec;
wire [19:0] ch8_dec;wire [7:0] ch1_sig;
wire [7:0] ch2_sig;
wire [7:0] ch3_sig;
wire [7:0] ch4_sig;
wire [7:0] ch5_sig;
wire [7:0] ch6_sig;
wire [7:0] ch7_sig;
wire [7:0] ch8_sig;ad7606 u1(.clk (clk),.rst_n (rst_n),.ad_data (ad_data),.ad_busy (ad_busy), .first_data (first_data), .ad_os (ad_os), .ad_cs (ad_cs),.ad_rd (ad_rd), .ad_reset (ad_reset),.ad_convstab (ad_convstab),.ad_ch1 (ad_ch1), //ch1 ad data 16bit.ad_ch2 (ad_ch2), //ch2 ad data 16bit.ad_ch3 (ad_ch3), //ch3 ad data 16bit.ad_ch4 (ad_ch4), //ch4 ad data 16bit.ad_ch5 (ad_ch5), //ch5 ad data 16bit.ad_ch6 (ad_ch6), //ch6 ad data 16bit.ad_ch7 (ad_ch7), //ch7 ad data 16bit.ad_ch8 (ad_ch8) //ch8 ad data 16bit);/**********电压转换程序***********/
volt_cal u2(.clk (clk),.ad_reset (ad_reset),.ad_ch1 (ad_ch1), //ch1 ad data 16bit (input).ad_ch2 (ad_ch2), //ch2 ad data 16bit (input).ad_ch3 (ad_ch3), //ch3 ad data 16bit (input).ad_ch4 (ad_ch4), //ch4 ad data 16bit (input).ad_ch5 (ad_ch5), //ch5 ad data 16bit (input).ad_ch6 (ad_ch6), //ch6 ad data 16bit (input).ad_ch7 (ad_ch7), //ch7 ad data 16bit (input).ad_ch8 (ad_ch8), //ch8 ad data 16bit (input).ch1_dec (ch1_dec), //ch1 ad voltage (output).ch2_dec (ch2_dec), //ch2 ad voltage (output).ch3_dec (ch3_dec), //ch3 ad voltage (output).ch4_dec (ch4_dec), //ch4 ad voltage (output).ch5_dec (ch5_dec), //ch5 ad voltage (output).ch6_dec (ch6_dec), //ch6 ad voltage (output).ch7_dec (ch7_dec), //ch7 ad voltage (output).ch8_dec (ch8_dec), //ch8 ad voltage (output).ch1_sig (ch1_sig), //ch1 ad 正负 (output).ch2_sig (ch2_sig), //ch2 ad 正负 (output).ch3_sig (ch3_sig), //ch3 ad 正负 (output).ch4_sig (ch4_sig), //ch4 ad 正负 (output).ch5_sig (ch5_sig), //ch5 ad 正负 (output).ch6_sig (ch6_sig), //ch6 ad 正负 (output).ch7_sig (ch7_sig), //ch7 ad 正负 (output).ch8_sig (ch8_sig) //ch8 ad 正负 (output));/**********AD数据Uart串口发送程序***********/
uart u3(.clk50 (clk), .reset_n (rst_n), .ch1_dec (ch1_dec), //ad1 BCD voltage.ch2_dec (ch2_dec), //ad2 BCD voltage.ch3_dec (ch3_dec), //ad3 BCD voltage.ch4_dec (ch4_dec), //ad4 BCD voltage.ch5_dec (ch5_dec), //ad5 BCD voltage.ch6_dec (ch6_dec), //ad6 BCD voltage.ch7_dec (ch7_dec), //ad7 BCD voltage.ch8_dec (ch8_dec), //ad8 BCD voltage .ch1_sig (ch1_sig), //ch1 ad 正负.ch2_sig (ch2_sig), //ch2 ad 正负.ch3_sig (ch3_sig), //ch3 ad 正负.ch4_sig (ch4_sig), //ch4 ad 正负.ch5_sig (ch5_sig), //ch5 ad 正负.ch6_sig (ch6_sig), //ch6 ad 正负.ch7_sig (ch7_sig), //ch7 ad 正负.ch8_sig (ch8_sig), //ch8 ad 正负 .tx (tx));
//实例化ila逻辑分析仪
ila_0 ila_0_inst (.clk (clk ), .probe0 (ad_ch1 ), .probe1 (ad_ch2 ),.probe2 (ad_data)
);endmodule新建ad7606.v
`timescale 1ns / 1ps
//
// Module Name: ad7606
//
module ad7606(input clk, //50mhzinput rst_n,input [15:0] ad_data, //ad7606 采样数据input ad_busy, //ad7606 忙标志位 input first_data, //ad7606 第一个数据标志位 output [2:0] ad_os, //ad7606 过采样倍率选择output reg ad_cs, //ad7606 AD csoutput reg ad_rd, //ad7606 AD data readoutput reg ad_reset, //ad7606 AD resetoutput reg ad_convstab, //ad7606 AD convert startoutput reg [15:0] ad_ch1, //AD第1通道的数据output reg [15:0] ad_ch2, //AD第2通道的数据output reg [15:0] ad_ch3, //AD第3通道的数据output reg [15:0] ad_ch4, //AD第4通道的数据output reg [15:0] ad_ch5, //AD第5通道的数据output reg [15:0] ad_ch6, //AD第6通道的数据output reg [15:0] ad_ch7, //AD第7通道的数据output reg [15:0] ad_ch8 //AD第8通道的数据 );reg [15:0] cnt;
reg [5:0] i;
reg [3:0] state;parameter IDLE=4'd0;
parameter AD_CONV=4'd1;
parameter Wait_1=4'd2;
parameter Wait_busy=4'd3;
parameter READ_CH1=4'd4;
parameter READ_CH2=4'd5;
parameter READ_CH3=4'd6;
parameter READ_CH4=4'd7;
parameter READ_CH5=4'd8;
parameter READ_CH6=4'd9;
parameter READ_CH7=4'd10;
parameter READ_CH8=4'd11;
parameter READ_DONE=4'd12;assign ad_os=3'b000;//AD 复位电路
always@(posedge clk)beginif(cnt<16'hffff) begincnt<=cnt+1;ad_reset<=1'b1;endelsead_reset<=1'b0; endalways @(posedge clk) beginif (ad_reset==1'b1) begin state<=IDLE; ad_ch1<=0;ad_ch2<=0;ad_ch3<=0;ad_ch4<=0;ad_ch5<=0;ad_ch6<=0;ad_ch7<=0;ad_ch8<=0;ad_cs<=1'b1;ad_rd<=1'b1; ad_convstab<=1'b1;i<=0;end else begincase(state)IDLE: beginad_cs<=1'b1;ad_rd<=1'b1; ad_convstab<=1'b1; if(i==20) begini<=0; state<=AD_CONV;endelse i<=i+1'b1;endAD_CONV: begin if(i==2) begin //等待2个clocki<=0; state<=Wait_1;ad_convstab<=1'b1; endelse begini<=i+1'b1;ad_convstab<=1'b0; //启动AD转换endendWait_1: begin if(i==5) begin //等待5个clock, 等待busy信号为高i<=0;state<=Wait_busy;endelse i<=i+1'b1;end Wait_busy: begin if(ad_busy==1'b0) begin //等待busy信号为低i<=0; state<=READ_CH1;endendREAD_CH1: begin ad_cs<=1'b0; //cs信号有效 if(i==3) beginad_rd<=1'b1;i<=0;ad_ch1<=ad_data; //读CH1state<=READ_CH2; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH2: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch2<=ad_data; //读CH2state<=READ_CH3; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH3: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch3<=ad_data; //读CH3state<=READ_CH4; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH4: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch4<=ad_data; //读CH4state<=READ_CH5; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH5: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch5<=ad_data; //读CH5state<=READ_CH6; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH6: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch6<=ad_data; //读CH6state<=READ_CH7; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH7: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch7<=ad_data; //读CH7state<=READ_CH8; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_CH8: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch8<=ad_data; //读CH8state<=READ_DONE; endelse beginad_rd<=1'b0; i<=i+1'b1;endendREAD_DONE:beginad_rd<=1'b1; ad_cs<=1'b1;state<=IDLE;end default: state<=IDLE;endcase end endendmodule新建bcd.v
module bcd(clk,hex,dec);input clk;
input [16:0] hex;
output [19:0] dec;wire [15:0] rrhex;
reg [3:0] rhex[3:0];reg [18:0] rhexd;
reg [13:0] rhexc;
reg [9:0] rhexb;
reg [3:0] rhexa;reg [5:0] resa,resb,resc,resd;
reg [3:0] rese;assign rrhex = hex[16] ? ~hex[15:0]+1'b1 : hex[15:0]; //去符号
assign dec = {rese,resd[3:0],resc[3:0],resb[3:0],resa[3:0]};always@(posedge clk) //第一级寄存器
beginrhex[3] <= rrhex[15:12];rhex[2] <= rrhex[11:8];rhex[1] <= rrhex[7:4];rhex[0] <= rrhex[3:0];
endalways@(posedge clk) //高4bit译码
begincase(rhex[3])4'h0: rhexd <= 19'h00000;4'h1: rhexd <= 19'h04096; //0x1000 -> 4096 (十进制)4'h2: rhexd <= 19'h08192; //0x2000 -> 8192 (十进制)4'h3: rhexd <= 19'h12288; //0x3000 -> 12288 (十进制)4'h4: rhexd <= 19'h16384; //0x4000 -> 16384 (十进制)4'h5: rhexd <= 19'h20480; //0x5000 -> 20480 (十进制)4'h6: rhexd <= 19'h24576; //0x6000 -> 24576 (十进制)4'h7: rhexd <= 19'h28672; //0x7000 -> 28672 (十进制)4'h8: rhexd <= 19'h32768; //0x8000 -> 32768 (十进制)4'h9: rhexd <= 19'h36864; //0x9000 -> 36864 (十进制)4'ha: rhexd <= 19'h40960; //0xa000 -> 40960 (十进制)4'hb: rhexd <= 19'h45056; //0xb000 -> 45056 (十进制)4'hc: rhexd <= 19'h49152; //0xc000 -> 49152 (十进制)4'hd: rhexd <= 19'h53248; //0xd000 -> 53248 (十进制)4'he: rhexd <= 19'h57344; //0xe000 -> 57344 (十进制) 4'hf: rhexd <= 19'h61440; //0xf000 -> 61440 (十进制) default: rhexd <= 19'h00000;endcase
endalways@(posedge clk) //次高4bit译码
begincase(rhex[2]) 4'h0: rhexc <= 14'h0000;4'h1: rhexc <= 14'h0256; //0x100 -> 256 (十进制)4'h2: rhexc <= 14'h0512; //0x200 -> 512 (十进制)4'h3: rhexc <= 14'h0768; //0x300 -> 768 (十进制)4'h4: rhexc <= 14'h1024; //0x400 -> 1024 (十进制)4'h5: rhexc <= 14'h1280; //0x500 -> 1280 (十进制)4'h6: rhexc <= 14'h1536; //0x600 -> 1536 (十进制)4'h7: rhexc <= 14'h1792; //0x700 -> 1792 (十进制)4'h8: rhexc <= 14'h2048; //0x800 -> 2048 (十进制)4'h9: rhexc <= 14'h2304; //0x900 -> 2304 (十进制)4'ha: rhexc <= 14'h2560; //0xA00 -> 2560 (十进制)4'hb: rhexc <= 14'h2816; //0xB00 -> 2816 (十进制)4'hc: rhexc <= 14'h3072; //0xC00 -> 3072 (十进制)4'hd: rhexc <= 14'h3328; //0xD00 -> 3328 (十进制)4'he: rhexc <= 14'h3584; //0xE00 -> 3584 (十进制)4'hf: rhexc <= 14'h3840; //0xF00 -> 3840 (十进制)default: rhexc <= 14'h0000;endcase
end always@(posedge clk)
begincase(rhex[1])4'h0: rhexb <= 10'h000;4'h1: rhexb <= 10'h016;4'h2: rhexb <= 10'h032;4'h3: rhexb <= 10'h048;4'h4: rhexb <= 10'h064;4'h5: rhexb <= 10'h080;4'h6: rhexb <= 10'h096;4'h7: rhexb <= 10'h112;4'h8: rhexb <= 10'h128;4'h9: rhexb <= 10'h144;4'ha: rhexb <= 10'h160;4'hb: rhexb <= 10'h176;4'hc: rhexb <= 10'h192;4'hd: rhexb <= 10'h208;4'he: rhexb <= 10'h224;4'hf: rhexb <= 10'h240;default: rhexb <= 10'h000;endcase
end always@(posedge clk)
beginrhexa <= rhex[0];
endalways@(posedge clk) //每个结果按同级单个bcd码相加,高一级的bcd码要加上低一级的进位,也就是高出4位的部分
begin resa = addbcd4(rhexa[3:0],rhexb[3:0],rhexc[3:0], rhexd[3:0]);resb = addbcd4(resa[5:4], rhexb[7:4],rhexc[7:4], rhexd[7:4]);resc = addbcd4(resb[5:4], rhexb[9:8],rhexc[11:8], rhexd[11:8]);resd = addbcd4(resc[5:4], 4'h0, rhexc[13:12],rhexd[15:12]);rese = resd[5:4] + rhexd[18:16];
endfunction [5:0] addbcd4;
input [3:0] add1,add2,add3,add4;
beginaddbcd4 = add1 + add2 + add3 + add4;if(addbcd4 > 6'h1d) //>29 最低有一个可能出现0xf,但由二进制转换而来的数在这里不会出现大于40的情况addbcd4 = addbcd4 + 5'h12;else if(addbcd4 > 5'h13) //>19对结果加12addbcd4 = addbcd4 + 4'hc;else if(addbcd4 > 4'h9) //>9对结果加6addbcd4 = addbcd4 + 4'h6;
end
endfunctionendmodule新建clkdiv.v
`timescale 1ns / 1ps
//
// Module Name: clkdiv
//
module clkdiv(clk50, clkout);
input clk50; //系统时钟
output clkout; //采样时钟输出
reg clkout;
reg [15:0] cnt;always @(posedge clk50) //分频进程
beginif(cnt == 16'd162)beginclkout <= 1'b1;cnt <= cnt + 16'd1;endelse if(cnt == 16'd325)beginclkout <= 1'b0;cnt <= 16'd0;endelsebegincnt <= cnt + 16'd1;end
end
endmodule
新建uart.v
`timescale 1ns / 1ps
//
//
module uart(input clk50, //50Mhz clockinput reset_n,input [19:0] ch1_dec,input [19:0] ch2_dec,input [19:0] ch3_dec,input [19:0] ch4_dec,input [19:0] ch5_dec,input [19:0] ch6_dec,input [19:0] ch7_dec,input [19:0] ch8_dec, input [7:0] ch1_sig,input [7:0] ch2_sig,input [7:0] ch3_sig,input [7:0] ch4_sig,input [7:0] ch5_sig,input [7:0] ch6_sig,input [7:0] ch7_sig,input [7:0] ch8_sig,output tx );/********************************************/
//存储待发送的串口信息
/********************************************/
reg [7:0] uart_ad [113:0]; //存储发送的ASIC字符always @(clk)
begin //定义发送的字符if(uart_stat==3'b000) beginuart_ad[0]<=65; //存储字符 A uart_ad[1]<=68; //存储字符 Duart_ad[2]<=49; //存储字符 1uart_ad[3]<=58; //存储字符 : uart_ad[4]<=ch1_sig; //存储字符 正负 uart_ad[5]<=ch1_dec[19:16] + 48; //存储字符 个位 uart_ad[6]<=46; //存储字符 . uart_ad[7]<=ch1_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[8]<=ch1_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[9]<=ch1_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[10]<=ch1_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[11]<=86; //存储字符 Vuart_ad[12]<=32; //存储字符 空格uart_ad[13]<=32; //存储字符 空格uart_ad[14]<=65; //存储字符 A uart_ad[15]<=68; //存储字符 Duart_ad[16]<=50; //存储字符 2uart_ad[17]<=58; //存储字符 : uart_ad[18]<=ch2_sig; //存储字符 正负 uart_ad[19]<=ch2_dec[19:16] + 48; //存储字符 个位 uart_ad[20]<=46; //存储字符 . uart_ad[21]<=ch2_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[22]<=ch2_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[23]<=ch2_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[24]<=ch2_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[25]<=86; //存储字符 Vuart_ad[26]<=32; //存储字符 空格uart_ad[27]<=32; //存储字符 空格uart_ad[28]<=65; //存储字符 A uart_ad[29]<=68; //存储字符 Duart_ad[30]<=51; //存储字符 3uart_ad[31]<=58; //存储字符 : uart_ad[32]<=ch3_sig; //存储字符 正负 uart_ad[33]<=ch3_dec[19:16] + 48; //存储字符 个位 uart_ad[34]<=46; //存储字符 . uart_ad[35]<=ch3_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[36]<=ch3_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[37]<=ch3_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[38]<=ch3_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[39]<=86; //存储字符 Vuart_ad[40]<=32; //存储字符 空格uart_ad[41]<=32; //存储字符 空格 uart_ad[42]<=65; //存储字符 A uart_ad[43]<=68; //存储字符 Duart_ad[44]<=52; //存储字符 4uart_ad[45]<=58; //存储字符 : uart_ad[46]<=ch4_sig; //存储字符 正负 uart_ad[47]<=ch4_dec[19:16] + 48; //存储字符 个位 uart_ad[48]<=46; //存储字符 . uart_ad[49]<=ch4_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[50]<=ch4_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[51]<=ch4_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[52]<=ch4_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[53]<=86; //存储字符 Vuart_ad[54]<=32; //存储字符 空格uart_ad[55]<=32; //存储字符 空格uart_ad[56]<=65; //存储字符 A uart_ad[57]<=68; //存储字符 Duart_ad[58]<=53; //存储字符 5uart_ad[59]<=58; //存储字符 : uart_ad[60]<=ch5_sig; //存储字符 正负 uart_ad[61]<=ch5_dec[19:16] + 48; //存储字符 个位 uart_ad[62]<=46; //存储字符 . uart_ad[63]<=ch5_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[64]<=ch5_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[65]<=ch5_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[66]<=ch5_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[67]<=86; //存储字符 Vuart_ad[68]<=32; //存储字符 空格uart_ad[69]<=32; //存储字符 空格uart_ad[70]<=65; //存储字符 A uart_ad[71]<=68; //存储字符 Duart_ad[72]<=54; //存储字符 6uart_ad[73]<=58; //存储字符 : uart_ad[74]<=ch6_sig; //存储字符 正负 uart_ad[75]<=ch6_dec[19:16] + 48; //存储字符 个位 uart_ad[76]<=46; //存储字符 . uart_ad[77]<=ch6_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[78]<=ch6_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[79]<=ch6_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[80]<=ch6_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[81]<=86; //存储字符 Vuart_ad[82]<=32; //存储字符 空格uart_ad[83]<=32; //存储字符 空格uart_ad[84]<=65; //存储字符 A uart_ad[85]<=68; //存储字符 Duart_ad[86]<=55; //存储字符 7uart_ad[87]<=58; //存储字符 : uart_ad[88]<=ch7_sig; //存储字符 正负 uart_ad[89]<=ch7_dec[19:16] + 48; //存储字符 个位 uart_ad[90]<=46; //存储字符 . uart_ad[91]<=ch7_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[92]<=ch7_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[93]<=ch7_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[94]<=ch7_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[95]<=86; //存储字符 Vuart_ad[96]<=32; //存储字符 空格uart_ad[97]<=32; //存储字符 空格 uart_ad[98]<=65; //存储字符 A uart_ad[99]<=68; //存储字符 Duart_ad[100]<=56; //存储字符 8uart_ad[101]<=58; //存储字符 : uart_ad[102]<=ch8_sig; //存储字符 正负 uart_ad[103]<=ch8_dec[19:16] + 48; //存储字符 个位 uart_ad[104]<=46; //存储字符 . uart_ad[105]<=ch8_dec[15:12] + 48; //存储字符 小数点后一位uart_ad[106]<=ch8_dec[11:8] + 48; //存储字符 小数点后二位uart_ad[107]<=ch8_dec[7:4] + 48; //存储字符 小数点后三位uart_ad[108]<=ch8_dec[3:0] + 48; //存储字符 小数点后四位uart_ad[109]<=86; //存储字符 Vuart_ad[110]<=32; //存储字符 空格uart_ad[111]<=32; //存储字符 空格 uart_ad[112]<=10; //换行符uart_ad[113]<=13; //回车符 end
end /********************************************/
//串口发送时间字符串uart_ad[0]~uart_ad[113]
/********************************************/
reg [15:0] uart_cnt;
reg [2:0] uart_stat;reg [7:0] txdata; //串口发送字符
reg wrsig; //串口发送有效信号reg [8:0] k;reg [15:0] Time_wait; always @(posedge clk )
beginif(!reset_n) begin uart_cnt<=0;uart_stat<=3'b000; k<=0;endelse begincase(uart_stat)3'b000: begin if (Time_wait == 16'hffff) begin //两条发送字符串之间的间隔时间uart_stat<=3'b001; Time_wait<=0;endelse beginuart_stat<=3'b000; Time_wait<=Time_wait + 1'b1;endend 3'b001: begin if (k == 113 ) begin //发送第114个字符 if(uart_cnt ==0) begintxdata <= uart_ad[113]; uart_cnt <= uart_cnt + 1'b1;wrsig <= 1'b1; end else if(uart_cnt ==254) begin//一个字节发送为168个时钟，这里等待255个时钟，保证一个数据发送完成uart_cnt <= 0;wrsig <= 1'b0; uart_stat <= 3'b010; k <= 0;endelse begin uart_cnt <= uart_cnt + 1'b1;wrsig <= 1'b0; endendelse begin //发送前113个字符 if(uart_cnt ==0) begin txdata <= uart_ad[k]; uart_cnt <= uart_cnt + 1'b1;wrsig <= 1'b1; end else if(uart_cnt ==254) begin//一个字节发送为168个时钟，这里等待255个时钟，保证一个数据发送完成uart_cnt <= 0;wrsig <= 1'b0; k <= k + 1'b1; endelse begin uart_cnt <= uart_cnt + 1'b1;wrsig <= 1'b0; endend end3'b010: begin //发送finish uart_stat <= 3'b000; enddefault:uart_stat <= 3'b000;endcase end
end/**********产生串口时钟***********/
clkdiv u0 (.clk50 (clk50), .clkout (clk) //串口发送时钟,波特率9600的16倍 );/*************串口发送程序************/
uarttx u1 (.clk (clk), .datain (txdata),.wrsig (wrsig), .idle (idle), .tx (tx) );endmodule新建uarttx.v
`timescale 1ns / 1ps
//
// Module Name: uarttx //
//
module uarttx(clk, datain, wrsig, idle, tx);
input clk; //UART时钟
input [7:0] datain; //需要发送的数据
input wrsig; //发送命令，上升沿有效
output idle; //线路状态指示，高为线路忙，低为线路空闲
output tx; //发送数据信号
reg idle, tx;
reg send;
reg wrsigbuf, wrsigrise;
reg presult;
reg[7:0] cnt; //计数器
parameter paritymode = 1'b0;//检测发送命令是否有效
always @(posedge clk)
beginwrsigbuf <= wrsig;wrsigrise <= (~wrsigbuf) & wrsig;
endalways @(posedge clk)
beginif (wrsigrise && (~idle)) //当发送命令有效且线路为空闲时，启动新的数据发送进程beginsend <= 1'b1;endelse if(cnt == 8'd168) //一帧资料发送结束beginsend <= 1'b0;end
endalways @(posedge clk)
beginif(send == 1'b1) begincase(cnt) //产生起始位8'd0: begintx <= 1'b0;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd16: begintx <= datain[0]; //发送数据0位presult <= datain[0]^paritymode;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd32: begintx <= datain[1]; //发送数据1位presult <= datain[1]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd48: begintx <= datain[2]; //发送数据2位presult <= datain[2]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd64: begintx <= datain[3]; //发送数据3位presult <= datain[3]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd80: begin tx <= datain[4]; //发送数据4位presult <= datain[4]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd96: begintx <= datain[5]; //发送数据5位presult <= datain[5]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd112: begintx <= datain[6]; //发送数据6位presult <= datain[6]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd128: begin tx <= datain[7]; //发送数据7位presult <= datain[7]^presult;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd144: begintx <= presult; //发送奇偶校验位presult <= datain[0]^paritymode;idle <= 1'b1;cnt <= cnt + 8'd1;end8'd160: begintx <= 1'b1; //发送停止位 idle <= 1'b1;cnt <= cnt + 8'd1;end8'd168: begintx <= 1'b1; idle <= 1'b0; //一帧资料发送结束cnt <= cnt + 8'd1;enddefault: begincnt <= cnt + 8'd1;endendcaseendelse begintx <= 1'b1;cnt <= 8'd0;idle <= 1'b0;end
end
endmodule新建volt_cal.v
`timescale 1ns / 1ps
//
// Module Name: volt_cal
//
module volt_cal(input clk, //50mhzinput ad_reset,input [15:0] ad_ch1, //AD第1通道的数据input [15:0] ad_ch2, //AD第2通道的数据input [15:0] ad_ch3, //AD第3通道的数据input [15:0] ad_ch4, //AD第4通道的数据input [15:0] ad_ch5, //AD第5通道的数据input [15:0] ad_ch6, //AD第6通道的数据input [15:0] ad_ch7, //AD第7通道的数据input [15:0] ad_ch8, //AD第8通道的数据 output [19:0] ch1_dec, //AD第1通道的十进制电压数据output [19:0] ch2_dec, //AD第1通道的十进制电压数据 output [19:0] ch3_dec, //AD第1通道的十进制电压数据output [19:0] ch4_dec, //AD第1通道的十进制电压数据 output [19:0] ch5_dec, //AD第1通道的十进制电压数据output [19:0] ch6_dec, //AD第1通道的十进制电压数据 output [19:0] ch7_dec, //AD第1通道的十进制电压数据output [19:0] ch8_dec, //AD第1通道的十进制电压数据 output reg [7:0] ch1_sig, //AD第1通道的数据正负字符output reg [7:0] ch2_sig, //AD第2通道的数据正负字符 output reg [7:0] ch3_sig, //AD第1通道的数据正负字符output reg [7:0] ch4_sig, //AD第2通道的数据正负字符 output reg [7:0] ch5_sig, //AD第1通道的数据正负字符output reg [7:0] ch6_sig, //AD第2通道的数据正负字符 output reg [7:0] ch7_sig, //AD第1通道的数据正负字符output reg [7:0] ch8_sig //AD第2通道的数据正负字符 );reg [15:0] ch1_reg;
reg [15:0] ch2_reg;
reg [15:0] ch3_reg;
reg [15:0] ch4_reg;
reg [15:0] ch5_reg;
reg [15:0] ch6_reg;
reg [15:0] ch7_reg;
reg [15:0] ch8_reg;reg [31:0] ch1_data_reg;
reg [31:0] ch2_data_reg;
reg [31:0] ch3_data_reg;
reg [31:0] ch4_data_reg;
reg [31:0] ch5_data_reg;
reg [31:0] ch6_data_reg;
reg [31:0] ch7_data_reg;
reg [31:0] ch8_data_reg;reg [31:0] ch1_vol;
reg [31:0] ch2_vol;
reg [31:0] ch3_vol;
reg [31:0] ch4_vol;
reg [31:0] ch5_vol;
reg [31:0] ch6_vol;
reg [31:0] ch7_vol;
reg [31:0] ch8_vol;//AD 电压换算
always @(posedge clk)
beginif(ad_reset == 1'b1) begin ch1_reg<=0;ch2_reg<=0;ch3_reg<=0;ch4_reg<=0;ch5_reg<=0;ch6_reg<=0;ch7_reg<=0;ch8_reg<=0;endelse begin//CH1数据/if(ad_ch1[15]==1'b1) begin //如果是负电压ch1_reg<=16'hffff-ad_ch1+1'b1;ch1_sig <= 45; //'-' asic码end else beginch1_reg<=ad_ch1;ch1_sig<=43; //'+' asic码 end //CH2数据/if(ad_ch2[15]==1'b1) begin //如果是负电压ch2_reg<=16'hffff-ad_ch2+1'b1;ch2_sig <= 45; //'-' asic码end else beginch2_reg<=ad_ch2;ch2_sig<=43; //'+' asic码 end //CH3数据/ if(ad_ch3[15]==1'b1) begin //如果是负电压ch3_reg<=16'hffff-ad_ch3+1'b1;ch3_sig <= 45; //'-' asic码end else beginch3_reg<=ad_ch3;ch3_sig<=43; //'+' asic码 end //CH4数据/if(ad_ch4[15]==1'b1) begin //如果是负电压ch4_reg<=16'h7ffff-ad_ch4+1'b1;ch4_sig <= 45; //'-' asic码end else beginch4_reg<=ad_ch4;ch4_sig<=43; //'+' asic码 end //CH5数据/if(ad_ch5[15]==1'b1) begin //如果是负电压ch5_reg<=16'hffff-ad_ch5+1'b1;ch5_sig <= 45; //'-' asic码end else beginch5_reg<=ad_ch5;ch5_sig<=43; //'+' asic码 end //CH6数据/ if(ad_ch6[15]==1'b1) begin //如果是负电压ch6_reg<=16'hffff-ad_ch6+1'b1;ch6_sig <= 45; //'-' asic码end else beginch6_reg<=ad_ch6;ch6_sig<=43; //'+' asic码 end //CH7数据/ if(ad_ch7[15]==1'b1) begin //如果是负电压ch7_reg<=16'h7ffff-ad_ch7+1'b1;ch7_sig <= 45; //'-' asic码end else beginch7_reg<=ad_ch7;ch7_sig<=43; //'+' asic码 end //CH8数据/ if(ad_ch8[15]==1'b1) begin //如果是负电压ch8_reg<=16'hffff-ad_ch8+1'b1;ch8_sig <= 45; //'-' asic码end else beginch8_reg<=ad_ch8;ch8_sig<=43; //'+' asic码 end end
end //AD 电压换算(1 LSB = 5V / 32758 = 0.15mV
always @(posedge clk)
beginif(ad_reset == 1'b1) begin ch1_data_reg<=0;ch2_data_reg<=0;ch3_data_reg<=0;ch4_data_reg<=0;ch5_data_reg<=0;ch6_data_reg<=0;ch7_data_reg<=0;ch8_data_reg<=0;ch1_vol<=0;ch2_vol<=0;ch3_vol<=0;ch4_vol<=0;ch5_vol<=0;ch6_vol<=0;ch7_vol<=0;ch8_vol<=0; endelse begin ch1_data_reg<=ch1_reg * 50000; ch2_data_reg<=ch2_reg * 50000;ch3_data_reg<=ch3_reg * 50000;ch4_data_reg<=ch4_reg * 50000;ch5_data_reg<=ch5_reg * 50000;ch6_data_reg<=ch6_reg * 50000;ch7_data_reg<=ch7_reg * 50000;ch8_data_reg<=ch8_reg * 50000; ch1_vol<=ch1_data_reg >>15;ch2_vol<=ch2_data_reg >>15;ch3_vol<=ch3_data_reg >>15;ch4_vol<=ch4_data_reg >>15;ch5_vol<=ch5_data_reg >>15;ch6_vol<=ch6_data_reg >>15;ch7_vol<=ch7_data_reg >>15;ch8_vol<=ch8_data_reg >>15;end end //16进制转化为十进制的
bcd bcd1_ist( .hex (ch1_vol[15:0]),.dec (ch1_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd2_ist( .hex (ch2_vol[15:0]),.dec (ch2_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd3_ist( .hex (ch3_vol[15:0]),.dec (ch3_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd4_ist( .hex (ch4_vol[15:0]),.dec (ch4_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd5_ist( .hex (ch5_vol[15:0]),.dec (ch5_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd6_ist( .hex (ch6_vol[15:0]),.dec (ch6_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd7_ist( .hex (ch7_vol[15:0]),.dec (ch7_dec),.clk (clk)); //16进制转化为十进制的
bcd bcd8_ist( .hex (ch8_vol[15:0]),.dec (ch8_dec),.clk (clk)); endmodule
添加在线逻辑分析仪
修改名字为ila_0,采用两路信号，Probes设置为2，Sample Data Depth指的是采用深度，设置的越高，采集的信号越多，同样消耗的资源也会越多。
在Probe_Ports页面，设置Probe的宽度，设置PROBEO位宽为32，用于采样timer_cnt，设置PROBE1位宽为4，用于采样地址和写入RAM的数据，点击OK，ADC的数据是16位
在ad706_test.v中添加逻辑分析仪
//实例化ila逻辑分析仪
ila_0 ila_0_inst (.clk (clk ), .probe0 (ad_ch1 ), .probe1 (ad_ch2 ),.probe2 (ad_data)
);
布局布线
查看管脚约束文件da7606.xdc
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[0]}]
set_property PACKAGE_PIN T12 [get_ports {ad_data[15]}]
set_property PACKAGE_PIN U12 [get_ports {ad_data[14]}]
set_property PACKAGE_PIN V12 [get_ports {ad_data[13]}]
set_property PACKAGE_PIN W13 [get_ports {ad_data[12]}]
set_property PACKAGE_PIN U13 [get_ports {ad_data[11]}]
set_property PACKAGE_PIN V13 [get_ports {ad_data[10]}]
set_property PACKAGE_PIN T14 [get_ports {ad_data[9]}]
set_property PACKAGE_PIN T15 [get_ports {ad_data[8]}]
set_property PACKAGE_PIN V17 [get_ports {ad_data[7]}]
set_property PACKAGE_PIN V18 [get_ports {ad_data[6]}]
set_property PACKAGE_PIN T16 [get_ports {ad_data[5]}]
set_property PACKAGE_PIN U17 [get_ports {ad_data[4]}]
set_property PACKAGE_PIN P15 [get_ports {ad_data[3]}]
set_property PACKAGE_PIN P16 [get_ports {ad_data[2]}]
set_property PACKAGE_PIN U14 [get_ports {ad_data[1]}]
set_property PACKAGE_PIN U15 [get_ports {ad_data[0]}]
set_property PACKAGE_PIN P14 [get_ports {ad_os[2]}]
set_property PACKAGE_PIN W19 [get_ports {ad_os[1]}]
set_property PACKAGE_PIN W18 [get_ports {ad_os[0]}]
set_property PACKAGE_PIN W15 [get_ports ad_busy]
set_property PACKAGE_PIN R14 [get_ports ad_convstab]
set_property PACKAGE_PIN V15 [get_ports ad_cs]
set_property PACKAGE_PIN Y17 [get_ports ad_rd]
set_property PACKAGE_PIN Y16 [get_ports ad_reset]
set_property PACKAGE_PIN W14 [get_ports first_data]
set_property PACKAGE_PIN N15 [get_ports rst_n]
set_property PACKAGE_PIN U18 [get_ports clk]
set_property PACKAGE_PIN F17 [get_ports tx]
set_property PACKAGE_PIN F16 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_os[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_os[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_os[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports ad_busy]
set_property IOSTANDARD LVCMOS33 [get_ports ad_convstab]
set_property IOSTANDARD LVCMOS33 [get_ports ad_cs]
set_property IOSTANDARD LVCMOS33 [get_ports ad_rd]
set_property IOSTANDARD LVCMOS33 [get_ports ad_reset]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports first_data]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk]
添加时序约束，点击Run synthesis 开始综合
点击“Constraints Wizard”
把"ys_clk"频率设置为50Mhz，然后点击Skip to finish结束时序约束向导
生成bitstream并下载bit文件到FPGA，通过ila观察AD7606的数据
查看的端口
